The quality of packaging directly affects the performance of electronic components and the design and manufacturing of PCBs connected to them, so packaging technology is crucial. Today, we will share common packaging methods for electronic components.
1. QFP Square Flatpack
The spacing between the pins of the packaged chip is very small, and the pins are very small. This packaging method is commonly used in large planning or ultra large integrated circuits, with a number of pins generally exceeding 100. The chip packaged in this way requires the use of SMD (Surface Assembly Equipment Skill) to solder the chip to the motherboard. Chips assembled with SMD do not need to be punched on the motherboard, as there are usually planned solder joints for response pins on the exterior of the motherboard. By aligning the pins of the chip with the corresponding solder joints, welding with the motherboard can be completed. A chip soldered on using this method is difficult to disassemble without the use of specialized tools.
For example, chips in Intel series CPUs such as 80286, 80386, and some 486 motherboards use this packaging.
2. DIP Dual Inline Packaging Technology
Dual in line packaging, a component packaging scenario for DRAM. Refers to integrated circuits and module power supplies packaged in a dual inline configuration. The vast majority of small and medium-sized integrated circuits and module power supplies use this packaging configuration, and the number of pins usually does not exceed 100. DIP packaging structures include multi-layer ceramic dual inline DIP, single-layer ceramic dual inline DIP, lead frame DIP, plastic packaging structure, ceramic low melting glass packaging, and so on.
3. PLCC plastic sealed lead chip packaging
The shape is square, surrounded by pins, and the size of the shape is much smaller than that of DIP packaging. PLCC packaging is suitable for assembly and wiring on PCBs using SMD surface assembly skills, with a small size and high reliability advantage.
4. BGA ball grid array package
The I/O terminals of BGA packaging are distributed below the packaging in an array of circular or columnar solder joints. The advantage of BGA skills is that although the number of I/O pins has been added, the pin spacing has not decreased, but has been added instead, thereby improving the assembly yield. Despite its increased power consumption, BGA can be soldered using a controllable collapse chip method, which can then improve its electric heating function. The thickness and quality of the packaging skills have been reduced compared to before, with reduced parasitic parameters, reduced delay in signal transmission, and increased frequency of use. Assembly can be done through coplanar welding, resulting in high reliability
5. SOP Small Outline Package
SOP packaging skills were successfully developed by Philips from 1968 to 1969, and gradually evolved into SOJ (J-pin small shape packaging), TSOP (thin small external packaging), VSOP (small external packaging), SSOP (reduced SOP), TSSOP (thin reduced SOP), SOT (small external transistor), SOIC (small external integrated circuit), etc. The application scale of SOP packaging is very wide, and the frequency generator chip of the motherboard is selected with SOP packaging.